Invention Grant
- Patent Title: Failing read count diagnostics for memory built-in self-test
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Application No.: US15894046Application Date: 2018-02-12
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Publication No.: US10593419B1Publication Date: 2020-03-17
- Inventor: Steven Lee Gregor , Puneet Arora , Norman Robert Card
- Applicant: Cadence Design Systems, Inc.
- Applicant Address: US CA San Jose
- Assignee: CADENCE DESIGN SYSTEMS, INC.
- Current Assignee: CADENCE DESIGN SYSTEMS, INC.
- Current Assignee Address: US CA San Jose
- Agency: Tarolli, Sundheim, Covell & Tummino LLP
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G11C29/38 ; G11C29/44 ; G11C29/36
Abstract:
Systems and methods disclosed herein provide for improved diagnostics for memory built-in self-test (“MBIST”). Embodiments provide for a sequence iterator unit including a diagnostics analysis unit that monitors and reports on the failing read count associated with the tested memory. Embodiments further provide for a bit fail map report that is generated based on the failing read count.
Information query
