Invention Grant
- Patent Title: Testing system for semiconductor package components and its thermal barrier layer element
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Application No.: US15798419Application Date: 2017-10-31
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Publication No.: US10598724B2Publication Date: 2020-03-24
- Inventor: Chih-Chieh Liao , Yu-Min Sun , Chih-Feng Cheng
- Applicant: GLOBAL UNICHIP CORPORATION , TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu TW Hsinchu
- Assignee: GLOBAL UNICHIP CORPORATION,TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: GLOBAL UNICHIP CORPORATION,TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu TW Hsinchu
- Agency: CKC & Partners Co., LLC
- Priority: CN201710748478 20170828
- Main IPC: G01R31/10
- IPC: G01R31/10 ; G01R31/28 ; G01R1/04

Abstract:
A testing system for semiconductor package components includes a testing circuit board, a test socket, at least one probe pin and a thermal barrier layer element. The testing circuit board has at least one electrical contact. The test socket is used to receive a DUT. The probe pin is located on the test socket for contacting with the DUT. The thermal barrier layer element is located between the testing circuit board and the test socket, electrically connected to the probe pin and the electrical contact, and thermally isolated the electrical contact from the probe pin.
Public/Granted literature
- US20190064258A1 TESTING SYSTEM FOR SEMICONDUCTOR PACKAGE COMPONENTS AND ITS THERMAL BARRIER LAYER ELEMENT Public/Granted day:2019-02-28
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