A tool for determining unknown sources in a circuit design for exclusion from logic built-in self test (LBIST) verification for the circuit. Responsive to initializing each of one or more latches in one or more test channels of the circuit design being tested, the tool determines whether a latch of the one or more latches is corrupted by an unknown source. The tool gathers each of the one or more latches determined to be an unknown source after a capture clock phase. The tool performs a backward traverse of logic circuitry feeding each of the one or more latches determined to be an unknown source. The tool verifies that a fence on one or more unknown source nets associated with each of the one or more latches blocked the unknown source from contributing to a test signature.