Invention Grant
- Patent Title: Method for determining sampling phase of sampling clock signal and associated electronic device
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Application No.: US15639049Application Date: 2017-06-30
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Publication No.: US10598776B2Publication Date: 2020-03-24
- Inventor: Ming-Han Weng , Wei-Yung Wang , Chih-Hung Lin , Jyun Yang Shih , Chun-Chia Chen
- Applicant: MStar Semiconductor, Inc.
- Applicant Address: TW Hsinchu
- Assignee: MEDIATEK INC.
- Current Assignee: MEDIATEK INC.
- Current Assignee Address: TW Hsinchu
- Agency: McClure, Qualey & Rodack, LLP
- Priority: TW106100102A 20170104
- Main IPC: H03K5/135
- IPC: H03K5/135 ; H03K5/151 ; H03L7/08 ; H03L7/091 ; G01S13/28 ; H04N7/18 ; G11C7/22

Abstract:
An electronic device includes a clock generating circuit, a receiving circuit and a training circuit. The clock generating circuit generates a sampling clock signal, a phase-early sampling clock signal and a phase-late sampling clock signal. The receiving circuit samples received data according to the sampling clock signal, the phase-early sampling clock signal and the phase-late sampling clock signal to generate a sample result. The training circuit controls the clock generating circuit to generate the sampling clock signal and the corresponding phase-early sampling clock signal and phase-late sampling clock signal that have different phases in a plurality of different time intervals, respectively, to cause the receiving circuit to generate a plurality of sample results. The training circuit further determines a sampling phase of the sampling clock signal according to the sample results.
Public/Granted literature
- US20180188364A1 METHOD FOR DETERMINING SAMPLING PHASE OF SAMPLING CLOCK SIGNAL AND ASSOCIATED ELECTRONIC DEVICE Public/Granted day:2018-07-05
Information query
IPC分类: