Invention Grant
- Patent Title: Critical methodology in vacuum chambers to determine gap and leveling between wafer and hardware components
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Application No.: US15675101Application Date: 2017-08-11
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Publication No.: US10599043B2Publication Date: 2020-03-24
- Inventor: Hiroyuki Ogiso , Jianhua Zhou , Zonghui Su , Juan Carlos Rocha-Alvarez , Jeongmin Lee , Karthik Thimmavajjula Narasimha , Rick Gilbert , Sang Heon Park , Abdul Aziz Khaja , Vinay Prabhakar
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: APPLIED MATERIALS, INC.
- Current Assignee: APPLIED MATERIALS, INC.
- Current Assignee Address: US CA Santa Clara
- Agency: Patterson + Sheridan LLP
- Main IPC: H01L21/26
- IPC: H01L21/26 ; H01L21/66 ; G03F7/20 ; G03F7/16 ; H01L21/02 ; H01L21/683 ; C23C16/52 ; H01L21/12

Abstract:
Implementations described herein generally relate to methods for leveling a component above a substrate. In one implementation, a test substrate is placed on a substrate support inside of a processing chamber. A component, such as a mask, is located above the substrate. The component is lowered to a position so that the component and the substrate are in contact. The component is then lifted and the particle distribution on the test substrate is reviewed. Based on the particle distribution, the component may be adjusted. A new test substrate is placed on the substrate support inside of the processing chamber, and the component is lowered to a position so that the component and the new test substrate are in contact. The particle distribution on the new test substrate is reviewed. The process may be repeated until a uniform particle distribution is shown on a test substrate.
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