An integer division circuit includes a first bit-shifting circuit configured to shift the bits of a dividend to produce a normalized dividend. The circuit also includes a second bit-shifting circuit configured to shift the bits of a divisor to produce a normalized divisor. A divider tree circuit is configured to divide the normalized dividend by the normalized divisor to produce a normalized quotient. The circuit further includes a third bit-shifting circuit configured to shift the bits of the normalized quotient to produce a quotient.