- Patent Title: Scheduling of threads for execution utilizing barrier usage data
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Application No.: US16388444Application Date: 2019-04-18
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Publication No.: US10599438B2Publication Date: 2020-03-24
- Inventor: Balaji Vembu , Abhishek R. Appu , Joydeep Ray , Altug Koker
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Jaffery Watson Mendonsa & Hamilton LLP
- Main IPC: G06T1/20
- IPC: G06T1/20 ; G06F9/50 ; G06F9/48 ; G06F9/38 ; G06F9/46 ; G06F9/52 ; G06F9/54 ; G06F15/16 ; G06F15/76 ; G06F12/0897 ; G06F12/0866 ; G06T1/60
Abstract:
An apparatus to facilitate thread scheduling is disclosed. The apparatus includes logic to store barrier usage data based on a magnitude of barrier messages in an application kernel and a scheduler to schedule execution of threads across a plurality of multiprocessors based on the barrier usage data.
Public/Granted literature
- US20190317771A1 GRAPHICS SCHEDULING MECHANISM Public/Granted day:2019-10-17
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