Invention Grant
- Patent Title: Instruction prefetch mechanism
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Application No.: US15670265Application Date: 2017-08-07
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Publication No.: US10599571B2Publication Date: 2020-03-24
- Inventor: Vasileios Porpodas , Guei-Yuan Lueh , Subramaniam Maiyuran , Wei-Yu Chen
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Jaffery Watson Mendonsa & Hamilton LLP
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F12/0862 ; G06F12/0875 ; G06F8/41

Abstract:
An apparatus to facilitate data prefetching is disclosed. The apparatus includes a cache, one or more execution units (EUs) to execute program code, prefetch logic to maintain tracking information of memory instructions in the program code that trigger a cache miss and compiler logic to receive the tracking information, insert one or more pre-fetch instructions in updated program code to prefetch data from a memory for execution of one or more of the memory instructions that triggered a cache miss and download the updated program code for execution by the one or more EUs.
Public/Granted literature
- US20190042433A1 INSTRUCTION PREFETCH MECHANISM Public/Granted day:2019-02-07
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