Techniques and systems for using a layer performance metric (LPM) during integrated circuit (IC) design are described. Some embodiments can compute an LPM value for at least one timing path in the IC design, wherein the LPM value is equal to a ratio between a wire length of the timing path and a delay of the timing path. Next, the embodiments can use the LPM value of the timing path to perform at least one of placement, routing, or optimization of the timing path.