Invention Grant
- Patent Title: Ternary content addressable memory with match line circuit for controlling potential of match realizing higher speed of search access
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Application No.: US15926863Application Date: 2018-03-20
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Publication No.: US10600483B2Publication Date: 2020-03-24
- Inventor: Makoto Yabuuchi
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: McDermott Will & Emery LLP
- Priority: JP2017-106507 20170530
- Main IPC: G11C15/04
- IPC: G11C15/04 ; G11C8/08 ; G11C11/412 ; G11C16/12 ; G11C8/14

Abstract:
An object of the present disclosure is to provide a content addressable memory realizing higher speed of a search access. A content addressable memory includes: a plurality of memory cells; a match line coupled to the plurality of memory cells; a search line coupled to each of the plurality of memory cells; a match line output circuit coupled to the match line; and a potential changing circuit coupled to the match line and changing the potential of the match line.
Public/Granted literature
- US20180350438A1 CONTENT ADDRESSABLE MEMORY AND SEMICONDUCTOR DEVICE Public/Granted day:2018-12-06
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