Invention Grant
- Patent Title: Memory system, reading method, program, and memory controller
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Application No.: US16120093Application Date: 2018-08-31
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Publication No.: US10600489B2Publication Date: 2020-03-24
- Inventor: Tomoya Kodama , Takayuki Itoh
- Applicant: TOSHIBA MEMORY CORPORATION
- Applicant Address: JP Tokyo
- Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Kim & Stewart LLP
- Priority: JP2018-041166 20180307
- Main IPC: G11C16/10
- IPC: G11C16/10 ; G11C16/34 ; G11C11/56 ; G11C16/26 ; G11C29/44 ; G11C8/12 ; G06K9/62 ; G11C29/42

Abstract:
According to one embodiment, a memory system includes memory cells capable of having data written therein at different write levels. A memory controller is configured to detect first data of the memory cells, then apply a first voltage that is lower than a voltage used for writing the data to the plurality of memory cells, detect second data of the memory cells after the first voltage has been applied, and estimate a write level for the data written to the memory cells based on a comparison of the first data and the second data.
Public/Granted literature
- US20190279728A1 MEMORY SYSTEM, READING METHOD, PROGRAM, AND MEMORY CONTROLLER Public/Granted day:2019-09-12
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