This application relates to the field of semiconductor technologies, and discloses a test structure and a manufacturing method therefor. Forms of the method may include: providing a top wafer structure, where the top wafer structure includes a top wafer and multiple first pads that are spaced from each other at a bottom of the top wafer; providing a bottom wafer structure, where the bottom wafer structure includes a bottom wafer and multiple second pads that are spaced from each other at a top of the bottom wafer, where a side surface of at least one of two adjacent second pads has an insulation layer; bonding the multiple first pads with the multiple second pads in a eutectic bonding manner, where each first pad is bonded with a second pad, to form multiple pads. This application may mitigate a problem that bonded pads are connected to each other.