- Patent Title: Bump-on-trace packaging structure and method for forming the same
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Application No.: US16050669Application Date: 2018-07-31
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Publication No.: US10600709B2Publication Date: 2020-03-24
- Inventor: Meng-Tse Chen , Wei-Hung Lin , Chih-Wei Lin , Kuei-Wei Huang , Hui-Min Huang , Ming-Da Cheng , Chung-Shi Liu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L23/31 ; H01L23/00 ; H01L23/498

Abstract:
A device comprises a first package component, and a first metal trace and a second metal trace on a top surface of the first package component. The device further includes a dielectric mask layer covering the top surface of the first package component, the first metal trace and the second metal trace, wherein the dielectric mask layer has an opening therein exposing the first metal trace. The device also includes a second package component and an interconnect formed on the second package component, the interconnect having a metal bump and a solder bump formed on the metal bump, wherein the solder bump contacts the first metal trace in the opening of the dielectric mask layer.
Public/Granted literature
- US20180337106A1 BUMP-ON-TRACE PACKAGING STRUCTURE AND METHOD FOR FORMING THE SAME Public/Granted day:2018-11-22
Information query
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