Methods, systems, and devices for compensating for memory input capacitance. Techniques are described herein to alter the capacitance of an access line coupled with a plurality of memory cells. The capacitance of the access line may be filtered by an inductive region, which could be implemented in one or more individual signal paths. Thus a signal may be transmitted to one or more selected memory cells and the inductive region may alter a capacitance of the access line in response to receiving a reflection of the signal from an unselected memory cell. In some examples, the transmitted signal may be modulated using pulse amplitude modulation (PAM), where the signal may be modulated using a modulation scheme that includes at least three levels to encode more than one bit of information (e.g., PAM4).