Invention Grant
- Patent Title: NOR memory cell with vertical floating gate
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Application No.: US16122800Application Date: 2018-09-05
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Publication No.: US10600797B2Publication Date: 2020-03-24
- Inventor: Bing Yeh
- Applicant: GREENLIANT IP, LLC
- Applicant Address: US CA Santa Clara
- Assignee: GREENLIANT IP LLC
- Current Assignee: GREENLIANT IP LLC
- Current Assignee Address: US CA Santa Clara
- Agency: Morgan, Lewis & Bockius LLP
- Main IPC: G11C16/04
- IPC: G11C16/04 ; H01L27/11556 ; H01L21/28 ; G11C16/26 ; H01L29/788 ; H01L27/11521 ; H01L29/66 ; G11C16/10 ; G11C16/14 ; G11C16/24 ; H01L23/522 ; H01L29/423

Abstract:
An electrically erasable programmable nonvolatile memory cell includes a semiconductor substrate having a first substrate region and a trench region apart from the first substrate region in a lateral direction, a channel region between the first substrate region and the bottom portion of the trench region, an electrically conductive control gate insulated from and disposed over the first channel portion, an electrically conductive floating gate insulated from the bottom and sidewall portions of the trench region, an insulation region disposed over the second channel portion between the control gate and the second floating gate portion, an electrically conductive source line insulated from the floating gate and electrically connected to the trench region of the substrate, and an electrically conductive erase gate insulated from and disposed over a tip of the floating gate.
Public/Granted literature
- US20190088668A1 NOR Memory Cell with Vertical Floating Gate Public/Granted day:2019-03-21
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