Invention Grant
- Patent Title: Self-clocking sampler with reduced metastability
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Application No.: US15693325Application Date: 2017-08-31
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Publication No.: US10601409B2Publication Date: 2020-03-24
- Inventor: John W. Poulton , Sudhir Shrikantha Kudva , Stephen G. Tell , John Michael Wilson
- Applicant: NVIDIA Corporation
- Applicant Address: US CA Santa Clara
- Assignee: NVIDIA Corporation
- Current Assignee: NVIDIA Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Leydig, Voit & Mayer, Ltd.
- Main IPC: H03K3/356
- IPC: H03K3/356 ; H03K5/135 ; H03K19/096 ; H02M3/156 ; G05F1/575

Abstract:
A circuit, method, and system are disclosed for sampling a signal. The system includes a sampler circuit configured to sample input signals when a clock signal is at a first level to produce sampled signals, a detection circuit that is coupled to the sampler circuit, and a feedback circuit that receives an output signal and generates the clock signal. The detection circuit pre-charges the sampled signals when the clock signal is at a second level and, using threshold adjusted inverters, detects voltage levels of each sampled signal to produce detected voltage level signals, where a threshold voltage of the threshold adjusted inverters is entirely outside of a transition voltage range of the sampler circuit. In response to one of the detected voltage level signals transitioning from the second level to the first level, the detection circuit transitions the output signal from the first level to the second level.
Public/Granted literature
- US20190068203A1 SELF-CLOCKING SAMPLER WITH REDUCED METASTABILITY Public/Granted day:2019-02-28
Information query
IPC分类: