Several embodiments of electrical circuit devices and systems with a duty cycle correction apparatus that includes a duty cycle adjustment circuit that is configured to adjust a duty cycle of the input clock signal based on an averaged code value. The duty cycle correction apparatus includes a duty cycle detector circuit that receives first and second clock signals from a clock distribution network. The duty cycle detector is configured to output a duty cycle status signal that indicates whether the first clock signal is above or below a 50% duty cycle based on a comparison of the first clock signal to the second clock signal. The duty cycle correction apparatus also includes a counter logic circuit configured to determine the average code value, and the counter logic circuit automatically cancels an offset of the duty cycle detector when determining the averaged code value.