Invention Grant
- Patent Title: Reduced latency error correction decoding
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Application No.: US15830526Application Date: 2017-12-04
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Publication No.: US10601448B2Publication Date: 2020-03-24
- Inventor: Glenn Gilda , Patrick J. Meaney , Arthur O'Neill , Barry M. Trager
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent William Kinnaman
- Main IPC: H03M13/15
- IPC: H03M13/15 ; H03M13/00

Abstract:
Systems, methods, and computer-readable media are disclosed for performing reduced latency error decoding using a reduced latency symbol error correction decoder that utilizes enumerated parallel multiplication in lieu of division and replaces general multiplication with constant multiplication. The use of parallel multiplication in lieu of division can provide reduced latency and replacement of general multiplication with constant multiplication allows for logic reduction. In addition, the reduced symbol error correction decoder can utilize decode term sharing which can yield a further reduction in decoder logic and a further latency improvement.
Public/Granted literature
- US20180367166A1 REDUCED LATENCY ERROR CORRECTION DECODING Public/Granted day:2018-12-20
Information query
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