Invention Grant
- Patent Title: Dynamic interleaver change for bit line failures in NAND flash storage
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Application No.: US16100952Application Date: 2018-08-10
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Publication No.: US10601546B2Publication Date: 2020-03-24
- Inventor: Naveen Kumar , Aman Bhatia , Yu Cai , Chenrong Xiong , Fan Zhang , Xuanxuan Lu
- Applicant: SK Hynix Inc.
- Applicant Address: KR Gyeonggi-do
- Assignee: SK Hynix Inc.
- Current Assignee: SK Hynix Inc.
- Current Assignee Address: KR Gyeonggi-do
- Agency: Kilpatrick Townsend & Stockton LLP
- Main IPC: H04L1/00
- IPC: H04L1/00 ; H03M13/27 ; G11C7/12

Abstract:
A dynamic interleaver performs a read operation to identify bit lines with high failures, and form groups of data bits for parity bits computation, such that each group includes at most one data bit from the bit lines with high failures. Thus, the interleave selects the bit lines with high failures based on a most recent read test, and can be adjusted according to the conditions of the storage device.
Public/Granted literature
- US20190305890A1 DYNAMIC INTERLEAVER CHANGE FOR BIT LINE FAILURES IN NAND FLASH STORAGE Public/Granted day:2019-10-03
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