In an embodiment, a processor may include a first clock circuit to generate a first clock signal, a plurality of functional blocks, and clock logic. Each functional block may include a sub-clock circuit to generate a second clock signal based on the first clock signal, and a counter to store a count of active consumer of the second clock signal. The clock logic may, in response to a determination that the counter of a first functional block has a value less than one, disable the sub-clock circuit of the first functional block. Other embodiments are described and claimed.