- Patent Title: Shell structure for insulation of a through-substrate interconnect
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Application No.: US15085925Application Date: 2016-03-30
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Publication No.: US10607885B2Publication Date: 2020-03-31
- Inventor: Tanay Karnik , William Wahby
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Womble Bond Dickinson (US) LLP
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/768 ; H01L23/528

Abstract:
Techniques and mechanisms for providing electrical insulation of a through-substrate interconnect (TI). In an embodiment, the TI extends between a first side of the substrate and a second side of the substrate opposite the first side. The substrate has formed therein a conductive shell structure that extends at least partially around a periphery of the TI. A first dielectric liner structure is disposed between the conductive shell structure and a bulk material of the substrate. A second dielectric liner structure is disposed between the conductive shell structure and the TI. In another embodiment, a voltage of the conductive shell structure is allowed to float while the TI exchanges a signal or a supply voltage.
Public/Granted literature
- US20170287781A1 SHELL STRUCTURE FOR INSULATION OF A THROUGH-SUBSTRATE INTERCONNECT Public/Granted day:2017-10-05
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