A standard cell architecture provides an improved immunity to power-supply voltage-drop, does not induce power-supply voltage drop on a continuous-row power rail of a standard cell, and maintains standard-cell environment compatibility. A circuit includes a first metal layer and a second metal layer that are formed different distances above a substrate. At least one first standard cell drives a first timing signal and includes at least one transistor receiving power from a first power rail in the first metal layer. At least one second standard cell drives a second timing signal and includes at least one transistor receiving power from a second power rail in the second metal layer. The second power rail has both a low peak noise level and a resistance that is lower than that of the first metal layer.