Invention Grant
- Patent Title: Relative frequency offset error and phase error detection for clocks
-
Application No.: US16194678Application Date: 2018-11-19
-
Publication No.: US10608649B1Publication Date: 2020-03-31
- Inventor: Kannanthodath V. Jayakumar , James David Barnette
- Applicant: Silicon Laboratories Inc.
- Applicant Address: US TX Austin
- Assignee: Silicon Laboratories Inc.
- Current Assignee: Silicon Laboratories Inc.
- Current Assignee Address: US TX Austin
- Agency: Zagorin Cave LLP
- Main IPC: H03L7/087
- IPC: H03L7/087 ; H03L7/18 ; H03L7/093 ; H03L7/089

Abstract:
An apparatus for providing a clock signal based on a received clock signal includes a time-to-digital converter configured to generate timestamp information based on the received clock signal. The apparatus includes a first filter configured to generate clock period information based on the timestamp information. The apparatus includes a phase monitor circuit. The phase monitor circuit includes a second filter configured to provide a mean period signal of the received clock signal based on the clock period information. The phase monitor includes a phase error detection circuit configured to generate a phase error indicator based on a threshold difference value and a difference between the clock period information and expected clock period information. The expected clock period information is based on the mean period signal.
Information query
IPC分类: