Provided is a recording head including: a recording element; a delay circuit including a delay element and configured to supply a clock signal from a main body unit of a recording apparatus to the delay element; and a logical sum (OR) element configured to generate a clock state signal based on a logical sum of the clock signal and output from each delay element. The recording head detects a defect in the clock signal transmitted from the main body unit to the recording head based on the clock state signal, and sets the recording element to a disable state when a defect is detected in the clock signal.