Invention Grant
- Patent Title: Logic built in self test circuitry for use in an integrated circuit with scan chains
-
Application No.: US14987945Application Date: 2016-01-05
-
Publication No.: US10649028B2Publication Date: 2020-05-12
- Inventor: Satya R. S. Bhamidipati , Raghu G. Gopalakrishnasetty , Mary P. Kusko , Cedric Lichtenau
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Margaret McNamara
- Main IPC: G01R31/3185
- IPC: G01R31/3185 ; G01R31/317

Abstract:
Aspects include a method for logic built-in self-testing (LBIST) for use in an integrated circuit with scan chains. The method includes programming a product control generator and a pattern generator with an LBIST pattern comprising at least a number of loops. The LBIST pattern is executed by generating scan-in test values for scan chains with the pattern generator and controlling at least one test parameter with the product control generator. Scan-out responses are collected from the scan chains in a signature register, and a start request is received from a chip tester. The LBIST is started in response to the start request. Test summary data is reported to the chip tester before the whole number of loops has been executed.
Public/Granted literature
- US20170192055A1 LOGIC BUILT IN SELF TEST CIRCUITRY FOR USE IN AN INTEGRATED CIRCUIT WITH SCAN CHAINS Public/Granted day:2017-07-06
Information query
IPC分类: