Invention Grant
- Patent Title: Silicon-on-insulator (SOI) die including a light emitting layer pedestal-aligned with a light receiving segment
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Application No.: US16391171Application Date: 2019-04-22
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Publication No.: US10649137B1Publication Date: 2020-05-12
- Inventor: Edward Preisler , Oleg Martynov , Farnood Rezaie
- Applicant: Newport Fab, LLC
- Applicant Address: US CA Newport Beach
- Assignee: Newport Fab, LLC
- Current Assignee: Newport Fab, LLC
- Current Assignee Address: US CA Newport Beach
- Agency: Farjami & Farjami LLP
- Main IPC: G02B6/12
- IPC: G02B6/12 ; G02B6/136 ; H01L25/16 ; G02B6/42

Abstract:
There are disclosed herein various implementations of a silicon-on-insulator (SOI) die including a light emitting layer pedestal-aligned with a light receiving segment, as well as methods for fabricating such an SOI die. The SOT die includes a pedestal region of the SOI die having a pedestal including a thin top silicon segment, a buried oxide (BOX) segment, and a handle wafer segment. The SOI die also includes an integrated circuit (IC) region having a thin silicon waveguide that is aligned with the thin top silicon segment in the pedestal region. A light emitting layer is situated over the pedestal in the pedestal region, the light emitting layer being aligned with the light receiving segment to situated over the thin silicon waveguide in the IC region.
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