Invention Grant
- Patent Title: Reduced stack usage in a multithreaded processor
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Application No.: US15367008Application Date: 2016-12-01
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Publication No.: US10649786B2Publication Date: 2020-05-12
- Inventor: Donald E. Steiss
- Applicant: Cisco Technology, Inc.
- Applicant Address: US CA San Jose
- Assignee: Cisco Technology, Inc.
- Current Assignee: Cisco Technology, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Patterson + Sheridan, LLP
- Main IPC: G06F9/38
- IPC: G06F9/38 ; G06F9/30 ; G06F9/50 ; G06F12/14 ; G06F12/1027

Abstract:
Embodiments are generally directed to a multithreaded processor for executing a plurality of threads, as well as an associated method and system. The multithreaded processor comprises a first control register configured to store a stack limit value, and instruction decode logic configured to, upon receiving a procedure entry instruction for a stack associated with a first thread, determine whether to throw a stack limit exception based on the stack limit value and a first predefined stack region size associated with the stack.
Public/Granted literature
- US20180157493A1 REDUCED STACK USAGE IN A MULTITHREADED PROCESSOR Public/Granted day:2018-06-07
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