The disclosure provides a processor, comprising at least one core. The core comprises an input buffer, a logic unit having an input and an output, wherein the input is in communication with the input buffer, and a memory unit in communication with the output of the logic unit. The processor also comprises a CU (Control Unit) configured to direct the operation of the core and a communication bus configured to interconnect the core and the CU. The CU is configured to direct the operation of the core by providing: an instruction to the core, wherein the instruction is loaded into the logic unit and writing to the input buffer a value stored in the memory unit of one of the cores; and an output of the instruction based at least partially on the value in the input buffer, and writing the output of the instruction to the memory unit.