A processor includes a memory-controller that controls an access to a memory which includes through electrode groups and a memory chip including a storage areas connected to each of the through-electrode groups including through-electrodes, and that includes an address-filter circuit that outputs an access address included in a read access request of reading data from the memory, as an error address, a counter that includes counters corresponding to the through-electrode groups and updates a counter value of the counter corresponding to the through-electrode group connected to the storage area indicated by the received error address, a first circuit that outputs area information indicating the storage area connected to the through-electrode group corresponding to the counter having a counter value which is greater than a predetermined value, and a second circuit that outputs an access request to the storage area indicated by the area information output from the first circuit.