A controller is configured to transmit a broadcast write request on at least one bus. The broadcast write request includes an address and a value. A first logic module determines that the broadcast write request is targeting the first logic module. The first logic module stores the value at a first addressed register specified by the register address. The second logic module determines that the broadcast write request is targeting the second logic module. The second logic module stores the value at a second addressed register specified by the register address. The first and second logic modules are connected to the at least one bus.