Invention Grant
- Patent Title: Spatial location of vias in a printed circuit board
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Application No.: US15711900Application Date: 2017-09-21
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Publication No.: US10650181B2Publication Date: 2020-05-12
- Inventor: Paul J. Brown , Alex L. Chan
- Applicant: NOKIA SOLUTIONS AND NETWORKS OY
- Applicant Address: FI Espoo
- Assignee: Nokia Solutions and Networks Oy
- Current Assignee: Nokia Solutions and Networks Oy
- Current Assignee Address: FI Espoo
- Agency: Kramer Amado, P.C.
- Main IPC: G06F30/39
- IPC: G06F30/39 ; G06F30/394 ; G06F17/50

Abstract:
A printed circuit board (PCB) having a layout aligned with a Ball Grid Array (BGA) package, the PCB including a plurality of victim vias arranged in the PCB, at least one aggressor via arranged in the PCB having a transition with at least one victim via, wherein the transition is a space in the PCB between a victim via and an aggressor via along a row direction or a column direction, and the victim via is not positioned next to more than one transition.
Public/Granted literature
- US20190087524A1 SPATIAL LOCATION OF VIAS IN A PRINTED CIRCUIT BOARD Public/Granted day:2019-03-21
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