Invention Grant
- Patent Title: Utilizing a distributed and parallel set of neurosynaptic core circuits for neuronal computation and non-neuronal computation
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Application No.: US14273487Application Date: 2014-05-08
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Publication No.: US10650301B2Publication Date: 2020-05-12
- Inventor: Rodrigo Alvarez-Icaza Rivera , Rathinakumar Appuswamy , John V. Arthur , Andrew S. Cassidy , Bryan L. Jackson , Paul A. Merolla , Dharmendra S. Modha , Jun Sawada
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Sherman IP LLP
- Agent Kenneth L. Sherman; Hemavathy Perumal
- Main IPC: G06N3/04
- IPC: G06N3/04 ; G06N3/063

Abstract:
Embodiments of the invention provide a neurosynaptic system comprising a delay unit for receiving and buffering axonal inputs, and a neural computation unit for generating neuronal outputs by performing a set of computations based on at least one axonal input received by the delay unit. The system further comprises a permutation unit for receiving external inputs to the system, and transmitting external outputs from the system. The permutation unit maps each external input received as either an axonal input to the delay unit or an external output from the system. The permutation unit maps each neuronal output generated by the neural computation unit as either an axonal input to the delay unit or an external output from the system. The neural computation unit comprises multiple electronic neurons, multiple electronic axons, and a plurality of electronic synapse devices interconnecting the neurons with the axons.
Public/Granted literature
- US20150324684A1 NEUROMORPHIC HARDWARE FOR NEURONAL COMPUTATION AND NON-NEURONAL COMPUTATION Public/Granted day:2015-11-12
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