A short circuit detector includes a first transistor connected between a first portion of a data line and a second portion of the data line and including a gate electrode connected to a first node; a second transistor connected between a first voltage source and the first node and including a gate electrode configured to receive a short-circuit test signal; a third transistor connected between a second node included in the second portion and a third node and including a gate electrode configured to receive the short-circuit test signal; a fourth transistor connected between a second voltage source and the first node and including a gate electrode connected to the third node; and a fifth transistor connected to the first node and a third voltage source and including a gate electrode connected to the third node in common with the gate electrode of the third transistor.