Tuning voltages in a read circuit
Abstract:
Techniques are provided for tuning the voltages of a circuit for reading a memory cell capable of storing three or more logic states. To read the memory cell, a charge may be transferred between a digit line and a sense component using a charge transfer device. The gate of the charge transfer device may initially be biased to a first voltage and subsequently tuned to a second voltage to optimize the sense window. After biasing the gate of the charge transfer device to the second voltage, the memory cell may discharge its charge onto the digit line, which may result in the digit line being biased to a third voltage. Based on whether the third voltage exceeds the second voltage, the charge transfer device may transfer the charge associated with the memory cell.
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