Invention Grant
- Patent Title: Planar integrated circuit package interconnects
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Application No.: US15198107Application Date: 2016-06-30
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Publication No.: US10651116B2Publication Date: 2020-05-12
- Inventor: Robert L. Sankman , Sanka Ganesan
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/498 ; H01L21/48 ; H01L21/56 ; H01L23/31

Abstract:
Generally discussed herein are systems, methods, and apparatuses that include conductive pillars that are about co-planar. According to an example, a technique can include growing conductive pillars on respective exposed landing pads of a substrate, situating molding material around and on the grown conductive pillars, removing, simultaneously, a portion of the grown conductive pillars and the molding material to make the grown conductive pillars and the molding material about planar, and electrically coupling a die to the conductive pillars.
Public/Granted literature
- US20180005928A1 PLANAR INTEGRATED CIRCUIT PACKAGE INTERCONNECTS Public/Granted day:2018-01-04
Information query
IPC分类: