Invention Grant
- Patent Title: Semiconductor device and method of forming wafer level ground plane and power ring
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Application No.: US15177081Application Date: 2016-06-08
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Publication No.: US10651139B2Publication Date: 2020-05-12
- Inventor: Guruprasad G. Badakere , Zigmund R. Camacho , Lionel Chien Hui Tay
- Applicant: STATS ChipPAC Pte. Ltd.
- Applicant Address: CN
- Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
- Current Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
- Current Assignee Address: CN
- Agency: Patent Law Group: Atkins and Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L23/528
- IPC: H01L23/528 ; H01L23/00 ; H01L23/31 ; H01L23/58 ; H01L21/56 ; H01L21/683

Abstract:
A semiconductor die has active circuits formed on its active surface. Contact pads are formed on the active surface of the semiconductor die and coupled to the active circuits. A die extension region is formed around a periphery of the semiconductor die. Conductive THVs are formed in the die extension region. A wafer level conductive plane or ring is formed on a center area of the active surface. The conductive plane or ring is connected to a first contact pad to provide a first power supply potential to the active circuits, and is electrically connected to a first conductive THV. A conductive ring is formed partially around a perimeter of the conductive plane or ring and connected to a second contact pad for providing a second power supply potential to the active circuits. The conductive ring is electrically connected to a second THV.
Public/Granted literature
- US20160293558A1 Semiconductor Device and Method of Forming Wafer Level Ground Plane and Power Ring Public/Granted day:2016-10-06
Information query
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