Invention Grant
- Patent Title: Staggered die stacking across heterogeneous modules
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Application No.: US16021351Application Date: 2018-06-28
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Publication No.: US10651148B2Publication Date: 2020-05-12
- Inventor: Yen Hsiang Chew
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwegman Lundberg & Woessner, P.A.
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@2398782
- Main IPC: H01L23/495
- IPC: H01L23/495 ; H01L25/065 ; H01L23/538 ; H01L23/31 ; H01L21/56 ; H01L25/00 ; H01L21/027 ; H01L25/10 ; H01L21/48

Abstract:
An electronic package can include a substrate, a first die and a second die. The first die can include a first thickness and the second die can include a second thickness. The first and second dies can be coupled to the substrate. A mold can be disposed on the substrate and cover the first die and the second die. The mold can include a planar upper surface. A first via, having a first length, can be extended between the first die and the planar upper surface. A second via, having a second length, can be extended between the second die and the planar upper surface. In some examples, a third die can be communicatively coupled to the first die using the first via and the second die using the second via.
Public/Granted literature
- US20190181118A1 STAGGERED DIE STACKING ACROSS HETEROGENEOUS MODULES Public/Granted day:2019-06-13
Information query
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