Invention Grant
- Patent Title: 3D circuit transistors with flipped gate
-
Application No.: US16196390Application Date: 2018-11-20
-
Publication No.: US10651202B2Publication Date: 2020-05-12
- Inventor: Francois Andrieu , Perrine Batude , Maud Vinet
- Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
- Applicant Address: FR Paris
- Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
- Current Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
- Current Assignee Address: FR Paris
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@56169ca3
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L21/84 ; H01L21/762 ; H01L23/528 ; H01L23/522 ; H01L27/06 ; H01L21/822 ; H01L27/088 ; H01L21/8234 ; H01L23/532 ; H01L21/033 ; H01L21/768 ; H01L21/285 ; H01L21/8238 ; H01L27/092
Abstract:
An integrated circuit is provided with several superimposed levels of transistors, the circuit including an upper level provided with transistors having a rear gate electrode laid out on a first semiconducting layer, and a second semiconducting layer, a first transistor among the transistors of the upper level being provided with a contact pad traversing the second semiconducting layer, the contact pad being connected to a connection zone disposed between the first semiconducting layer and the second semiconducting layer, the first transistor being polarised by and connected to at least one power supply line disposed on a side of a front face of the second semiconducting layer that is opposite to the rear face.
Public/Granted literature
- US20190157300A1 3D CIRCUIT TRANSISTORS WITH FLIPPED GATE Public/Granted day:2019-05-23
Information query
IPC分类:
