Invention Grant
- Patent Title: Self aligned top extension formation for vertical transistors
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Application No.: US16043637Application Date: 2018-07-24
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Publication No.: US10651308B2Publication Date: 2020-05-12
- Inventor: Oleg Gluschenkov , Sanjay C. Mehta , Shogo Mochizuki , Alexander Reznicek
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Tutunjian & Bitetto, P.C.
- Agent Daniel P. Morris
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L29/78 ; H01L29/66 ; H01L21/265 ; H01L21/306 ; H01L21/02 ; H01L29/08 ; H01L29/10 ; H01L29/165

Abstract:
A method of forming a semiconductor device that includes providing a vertically orientated channel region; and converting a portion of an exposed source/drain contact surface of the vertically orientated channel region into an amorphous crystalline structure. The amorphous crystalline structure is from the vertically orientated channel region. An in-situ doped extension region is epitaxially formed on an exposed surface of the vertically orientated channel region. A source/drain region is epitaxially formed on the in-situ doped extension region.
Public/Granted literature
- US20180331216A1 SELF ALIGNED TOP EXTENSION FORMATION FOR VERTICAL TRANSISTORS Public/Granted day:2018-11-15
Information query
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