An image processing apparatus of an embodiment includes: a distortion correction circuit configured to perform a correction operation to a plurality of pixels composing an input image; a plurality of output buffers layered to two or more stages configured to receive an output of the distortion correction circuit, and perform output for each transmission block which is a set of pixels with the consecutive corrected pixel positions; and a controller configured to write an output pixel of the distortion correction circuit in the first-stage output buffer, sequentially transfer the written pixel to a post-stage output buffer, and cause output buffers at respective stages to store pixels of sub-blocks into which the transmission block is divided.