Invention Grant
- Patent Title: Using runtime information from solvers to measure quality of formal verification
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Application No.: US16023849Application Date: 2018-06-29
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Publication No.: US10657307B1Publication Date: 2020-05-19
- Inventor: Himanshu Jain , Per M. Bjesse , Pratik Mahajan
- Applicant: Synopsys, Inc.
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Park, Vaughan, Fleming & Dowler LLP
- Agent Laxman Sahasrabuddhe
- Main IPC: G06F30/00
- IPC: G06F30/00 ; G06F30/3323 ; G06F30/30

Abstract:
Systems and techniques are described for using runtime information to identify a verification hole and/or compute a verification metric. Runtime information (RI) for a set of proven assertions can be determined, wherein the RI includes a first set of registers, a first set of inputs, and a first set of constraints that were used by a formal verification engine during runtime to prove one or more assertions for a design under verification (DUV). Next, a second set of registers, a second set of inputs, and a second set of constraints that are not present in the RI can be determined. The second set of registers, the second set of inputs, and/or the second set of constraints can then be used to (1) identify a verification hole and/or (2) compute a verification metric.
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