Invention Grant
- Patent Title: Semiconductor memory device having memory cell pairs defining data based on threshold voltages
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Application No.: US16112655Application Date: 2018-08-25
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Publication No.: US10658031B2Publication Date: 2020-05-19
- Inventor: Hirokazu Nagase
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Tokyo
- Agency: SGPatents PLLC
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@61d7bcbd
- Main IPC: G11C11/56
- IPC: G11C11/56 ; G11C16/32 ; G11C16/34

Abstract:
To provide a semiconductor memory device capable of storing multi-value data while suppressing an increase in the threshold voltage set for a memory cell. A semiconductor memory device according to an embodiment includes a plurality of memory cell pairs, each having a first memory cell and a second memory cell. The first memory cell is configured so as to set at least one threshold voltage, whereas the second memory cell is configured so as to set a plurality of threshold voltages. Data stored in the memory cell pairs is defined using differences between the threshold voltages of the second memory cell and the threshold voltage of the first memory cell.
Public/Granted literature
- US20190139601A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DEFINING DATA IN SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2019-05-09
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