Invention Grant
- Patent Title: Bit error rate estimation for NAND flash memory
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Application No.: US16525409Application Date: 2019-07-29
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Publication No.: US10658058B1Publication Date: 2020-05-19
- Inventor: Yasuhiko Kurosawa , Avi Steiner , Hanan Weingarten
- Applicant: Toshiba Memory Corporation
- Applicant Address: JP Tokyo
- Assignee: Toshiba Memory Corporation
- Current Assignee: Toshiba Memory Corporation
- Current Assignee Address: JP Tokyo
- Agency: Foley & Lardner LLP
- Main IPC: G11C16/06
- IPC: G11C16/06 ; G11C16/34 ; G11C16/12 ; G11C29/52
Abstract:
The present embodiments relate to methods for estimating bit error rates (BERs) associated with a flash memory. According to certain aspects, embodiments provide estimating the BER of multi-bit flash memories during the programming of the flash memory, and providing the estimated BER in a readable status register of the flash memory, thereby improving the speed of programming of the flash memory.
Information query
