Invention Grant
- Patent Title: Semiconductor memory device including a correcting circuit
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Application No.: US16123558Application Date: 2018-09-06
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Publication No.: US10658063B2Publication Date: 2020-05-19
- Inventor: Hiromi Noro , Kenji Tsuchida
- Applicant: TOSHIBA MEMORY CORPORATION
- Applicant Address: JP Tokyo
- Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Holtz, Holtz & Volek PC
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@21512b15
- Main IPC: G11C16/04
- IPC: G11C16/04 ; G11C29/04 ; G11C11/16 ; G11C29/52

Abstract:
According to one embodiment, a semiconductor memory device includes a memory cell, a read circuit, a correcting circuit and a write circuit. The read circuit is configured to read first data from the memory cell by receiving a first command. The correcting circuit is configured to generate second data by correcting an error included in the first data. The write circuit is configured to write the second data to the memory cell in response to receiving a second command.
Public/Granted literature
- US20190130986A1 SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2019-05-02
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