Invention Grant
- Patent Title: Dielectric damage-free dual damascene Cu interconnects without barrier at via bottom
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Application No.: US16163256Application Date: 2018-10-17
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Publication No.: US10658233B2Publication Date: 2020-05-19
- Inventor: Koichi Motoyama , Benjamin D. Briggs , Gangadhara Raja Muthinti , Cornelius Brown Peethala , Lawrence A. Clevenger
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Michael J. Chang, LLC
- Agent Vazken Alexanian
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/522 ; H01L23/532

Abstract:
Techniques for dielectric damage-free interconnects are provided. In one aspect, a method for forming a Cu interconnect structure includes: forming a via and trench in a dielectric over a metal line M1; depositing a first barrier layer into the via and trench; removing the first barrier layer from the via and trench bottoms using neutral beam oxidation, and removing oxidized portions of the first barrier layer such that the first barrier layer remains along only sidewalls of the via and trench; depositing Cu into the via in direct contact with the metal line M1 to form a via V1; lining the trench with a second barrier layer; and depositing Cu into the trench to form a metal line M2. The second barrier layer can instead include Mn or optionally CuMn so as to further serve as a seed layer. A Cu interconnect structure is also provided.
Information query
IPC分类: