Invention Grant
- Patent Title: Manufacturing methods for low temperature poly-silicon array substrate and low temperature poly-silicon thin-film transistor
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Application No.: US15737131Application Date: 2017-09-21
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Publication No.: US10658402B2Publication Date: 2020-05-19
- Inventor: Chen Chen
- Applicant: Wuhan China Star Optoelectronics Technology Co., Ltd.
- Applicant Address: CN Wuhan
- Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
- Current Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
- Current Assignee Address: CN Wuhan
- Agency: Brinks Gilson & Lione
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@458c24f5
- International Application: PCT/CN2017/102658 WO 20170921
- International Announcement: WO2019/024195 WO 20190207
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L21/77 ; H01L29/66 ; H01L29/786

Abstract:
Manufacturing methods for a low temperature poly-silicon array substrate and for a low temperature poly-silicon thin-film transistor are provided. The manufacturing method for the low temperature poly-silicon array substrate includes: providing a substrate; forming a poly-silicon semiconductor pattern on the substrate; a first channel region, a first source region and a first drain region being formed on a first portion of the poly-silicon semiconductor pattern that corresponds to the first thin-film transistor and a second thin-film transistor; forming a gate insulation layer; performing an activation treatment; forming a gate on the gate insulation layer after the activation treatment; forming an interlayer insulation layer between the gate insulation layer and the gate; performing a hydrogen treatment; forming a source/drain pattern on the interlayer insulation layer after the hydrogen treatment, and connecting the source/drain pattern to the source region and the drain region in the poly-silicon semiconductor pattern via a through hole.
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