Structures and/or methods that facilitate self-aligned gate cut on a dielectric fin extension in direct stacked vertical transport field effect transistor (VTFET). A semiconductor structure can comprise a silicon on insulator (SOI) semiconductor fin comprising a dielectric fin extension. The semiconductor structure can further comprise a first vertical transport field effect transistor (VTFET) comprising a first self-aligned gate on the dielectric fin extension. The semiconductor structure can further comprise a second VTFET comprising a second self-aligned gate on the dielectric fin extension. The semiconductor structure can further comprise a gate contact extending through the dielectric fin extension through the second VTFET to the first self-aligned gate.