Gate spacer and inner spacer formation for nanosheet transistors having relatively small space between gates
Abstract:
Embodiments of the invention are directed to a nano sheet field effect transistor (FET) device that includes a gate spacer and an inner spacer. The gate spacer includes an upper segment and a lower segment. The inner spacer has a first selectivity to etch compositions used in predetermined fabrication operations for forming the inner spacer. The lower segment has the first selectivity to etch compositions used in predetermined fabrication operations for forming the inner spacer. The upper segment has a second selectivity to etch compositions used in predetermined fabrication operations for forming the inner spacer. The first etch selectivity is greater than the second etch selectivity.
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