Invention Grant
- Patent Title: Transistors and methods of forming transistors using vertical nanowires
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Application No.: US15433141Application Date: 2017-02-15
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Publication No.: US10658494B2Publication Date: 2020-05-19
- Inventor: Dominic J. Schepis , Alexander Reznicek
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Thompson Hine LLP
- Agent Francois Pagette
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/786 ; H01L29/423 ; H01L29/78 ; H01L29/06 ; H01L29/51 ; H01L29/49

Abstract:
Devices and methods of fabricating vertical nanowires on semiconductor devices are provided. One method includes: obtaining an intermediate semiconductor device having a substrate, a first insulator disposed above the substrate, a material layer over the first insulator, a second insulator above the material layer, and a first hardmask; etching a plurality of vertical trenches through the hardmask, the first and second insulators, and the material layer; growing, epitaxially, a set of silicon nanowires from a bottom surface of the plurality of vertical trenches; etching a first set of vertical trenches to expose the material layer; etching a second set of vertical trenches to the substrate; depositing an insulating spacer material on a set of sidewalls of the first and second set of vertical trenches; and forming contacts in the first and second set of vertical trenches.
Public/Granted literature
- US20180233583A1 TRANSISTORS AND METHODS OF FORMING TRANSISTORS USING VERTICAL NANOWIRES Public/Granted day:2018-08-16
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