Method and Apparatus for automatically switching to a low power retention mode based on architectural clock gating is disclosed. In some implementations, a system includes a central processing unit (CPU), comprising a clock gating cell configured to receive a clock enable signal. The system further includes a switching module configured to monitor the clock enable signal and to cause a power manager to switch the CPU from a first power supply output to a second power supply output in response to the clock enable signal changing from a first state to a second state.